Embodiments of the present invention relate generally to image sensors, image sensor architecture, and pixel circuits; more particularly, some embodiments relate to systems and methods for charge-domain binning in an image sensor.
In an image sensor, pixel binning (i.e., combining signals of two or more pixels of an image sensor) in the charge-domain is known to provide for increasing the signal-to-noise ratio as well as for increasing the frame rate for a given pixel array readout bandwidth or, correspondingly, decreasing the pixel array readout bandwidth requirements for a given frame rate. In a CMOS image sensor, charge-domain binning may be implemented in a non-shared pixel architecture, in which each pixel includes dedicated readout circuitry (though pixels may selectively share, for example, a charge storage regions when binning charge), or in a shared pixel architecture, in which each group of two or more pixels may share at least some pixel circuitry, such as one or more of the following: a reset transistor, a floating diffusion, a source-follower transistor, and a row select transistor.
Some shared as well as non-shared pixel architectures configured for charge-domain binning may provide for selectively reading out one or more rows of pixels in either a charge-domain binning mode (e.g., each pixel in the row is binned with one or more pixels in the same row and/or one or more pixel in at least one other row) or a non-binning mode (i.e., individual pixels are readout separately). In addition, some architectures provide for selecting among two or more binning modes, such as 1×2, 2×1, 2×2 binning (using the typical convention of m×n binning meaning the combination of m pixels in the horizontal (row) direction and n pixels in the vertical (column) direction), same color binning (e.g., combining pixels of the same color over a neighborhood of pixels corresponding to the color filter array (CFA) pattern), etc.
Such selective charge-domain binning may be based on timing control and/or on in-pixel switchable reconfiguration of the pixel circuitry. For instance, in a shared pixel architecture having pixels that are hardwired to share a common floating diffusion, the pixels may be read out separately by time-multiplexing each pixel's charge transfer to the common floating diffusion while resetting the floating diffusion in advance of transferring each pixel's charge to the floating diffusion. To bin these shared pixels, their respective charge may be transferred to the common floating diffusion either successively, without resetting the floating diffusion between charge transfers, or simultaneously.
Selective binning based on switchable reconfiguration may employ pixels with respective isolated floating diffusion regions that may be selectively conductively connected using switches (e.g., transistors). For binning a given pair of pixels, their respective floating diffusions may be conductively coupled via a switch, and their charge may be transferred to the common floating diffusion either successively, without resetting the floating diffusion between charge transfers, or simultaneously. These pixels may be readout individually by deactivating the transistor (driving it “off,” to an open state) to isolate the respective floating diffusions in advance of charge being transferred thereto. While it is possible through timing control, similar to that described above for pixels with hardwired floating diffusions, to readout the pixels individually even when their floating diffusions are electrically connected via the switch, typically that is not done because the selective electrical connection of the floating diffusions is usually employed to scale the effective conversion gain inversely with the number of pixels being binned. As such, when a pixel is to be readout individually, the associated conversion gain for reading out the pixel is increased by opening the associated switch(es) to isolate the pixel's floating diffusion from the floating diffusion(s) selectively coupled thereto via the switch(es).
Such CMOS image sensor architectures that provide for pixel binning are configured such that for each row of a given frame, all of the pixels that are readout from the row are necessarily readout in the same mode, namely, either in a non-binning mode or in a particular binning mode. For instance, in CMOS image sensors having only one binning readout mode (e.g., 2×2), for a given frame, all the pixels readout from a given row are readout in either the non-binning mode or the binning mode. In addition, in configurations permitting more than one binning mode, all of the pixels for a row that is readout in a binning mode are readout in the same binning mode (e.g., all pixels are readout in a 1×2, 2×1, or 2×2 binning mode, exclusively). In other words, CMOS image sensors are configured such that different pixels readout from the same row for a frame cannot be readout in different modes.